Phase/Interfacial-Engineered Two-Dimensional-Layered WSe2 Films by a Plasma-Assisted Selenization Process: Modulation of Oxygen Vacancies in Resistive Random-Access Memory.

Here, we propose phase and interfacial engineering by inserting a functional WO3 layer and selenized it to achieve a 2D-layered WSe2/WO3 heterolayer structure by a plasma-assisted selenization process. The 2D-layered WSe2/WO3 heterolayer was coupled with an Al2O3 film as a resistive switching (RS) layer to form a hybrid structure, with which Pt and W films were used as the top and bottom electrodes, respectively. The device with good uniformity in SET/RESET voltage and high low-/high-resistance window can be obtained by controlling a conversion ratio from a WO3 film to a 2D-layered WSe2 thin film. The Pt/Al2O3/(2D-layered WSe2/WO3)/W structure shows remarkable improvement to the pristine Pt/Al2O3/W and Pt/Al2O3/2D-layered WO3/W in terms of low SET/RESET voltage variability (-20/20)%, multilevel characteristics (uniform LRS/HRS distribution), high on/off ratio (104-105), and retention (∼105 s). The thickness of the obtained WSe2 was tuned at different gas ratios to optimize different 2D-layered WSe2/WO3 (%) ratios, showing a distinctive trend of reduced and uniform SET/RESET voltage variability as 2D-layered WSe2/WO3 (%) changes from 90/10 (%) to 45/55 (%), respectively. The electrical measurements confirm the superior ability of the metallic 1T phase of the 2D-layered WSe2 over the semiconducting 2H phase. Through systemic studies of RS behaviors on the effect of 1T/2H phases and 2D-layered WSe2/WO3 ratios, the low-temperature plasma-assisted selenization offers compatibility with the temperature-limited 3D integration process and also provides much better thickness control over a large area.

Defect-engineered room temperature negative differential resistance in monolayer MoS2 transistors.

The negative differential resistance (NDR) effect has been widely investigated for the development of various electronic devices. Apart from traditional semiconductor-based devices, two-dimensional (2D) transition metal dichalcogenide (TMD)-based field-effect transistors (FETs) have also recently exhibited NDR behavior in several of their heterostructures. However, to observe NDR in the form of monolayer MoS2, theoretical prediction has revealed that the material should be more profoundly affected by sulfur (S) vacancy defects. In this work, monolayer MoS2 FETs with a specific amount of S-vacancy defects are fabricated using three approaches, namely chemical treatment (KOH solution), physical treatment (electron beam bombardment), and as-grown MoS2. Based on systematic studies on the correlation of the S-vacancies with both the device's electron transport characteristics and spectroscopic analysis, the NDR has been clearly observed in the defect-engineered monolayer MoS2 FETs with an S-vacancy (VS) amount of ∼5 ± 0.5%. Consequently, stable NDR behavior can be observed at room temperature, and its peak-to-valley ratio can also be effectively modulated via the gate electric field and light intensity. Through these results, it is envisioned that more electronic applications based on defect-engineered layered TMDs will emerge in the near future.

Voltage-Time Transformation Model for Threshold Switching Spiking Neuron Based on Nucleation Theory.

In this study, we constructed a voltage-time transformation model (V-t Model) to predict and simulate the spiking behavior of threshold-switching selector-based neurons (TS neurons). The V-t Model combines the physical nucleation theory and the resistor-capacitor (RC) equivalent circuit and successfully depicts the history-dependent threshold voltage of TS selectors, which has not yet been modeled in TS neurons. Moreover, based on our model, we analyzed the currently reported TS devices, including ovonic threshold switching (OTS), insulator-metal transition, and silver- (Ag-) based selectors, and compared the behaviors of the predicted neurons. The results suggest that the OTS neuron is the most promising and potentially achieves the highest spike frequency of GHz and the lowest operating voltage and area overhead. The proposed V-t Model provides an engineering pathway toward the future development of TS neurons for neuromorphic computing applications.

Bi2O2Se-Based True Random Number Generator for Security Applications.

The fast development of the Internet of things (IoT) promises to deliver convenience to human life. However, a huge amount of the data is constantly generated, transmitted, processed, and stored, posing significant security challenges. The currently available security protocols and encryption techniques are mostly based on software algorithms and pseudorandom number generators that are vulnerable to attacks. A true random number generator (TRNG) based on devices using stochastically physical phenomena has been proposed for auditory data encryption and trusted communication. In the current study, a Bi2O2Se-based memristive TRNG is demonstrated for security applications. Compared with traditional metal-insulator-metal based memristors, or other two-dimensional material-based memristors, the Bi2O2Se layer as electrode with non-van der Waals interface, high carrier mobility, air stability, extreme low thermal conductivity, as well as vertical surface resistive switching shows intrinsic stochasticity and complexity in a memristive true analogue/digital random number generation. Moreover, those analogue/digital random number generation processes are proved to be resilient for machine learning prediction.

Device quantization policy in variation-aware in-memory computing design.

Device quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (< 10) are less concerned.

2D Materials-Based Static Random-Access Memory.

2D transition-metal dichalcogenide semiconductors, such as MoS2 and WSe2 , with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)-based field-effect transistor (FET) and static random-access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read-write conflict in an SRAM cell at scaled technology nodes (1-2.1 nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time than the bilayer and trilayer 2DM SRAM cells at fixed leakage power. This simulation predicts that the optimization of 2DM SRAM designed with state-of-the-art contact resistance, mobility, and equivalent oxide thickness leads to excellent stability and operation speed at the 1-nm node. Applying the nanosheet (NS) gate-all-around (GAA) structure to 2DM further reduces cell read access time and write time and improves the area density of the SRAM cells, demonstrating a feasible scaling path beyond Si technology using 2DM NSFETs. In addition to the device design, the process challenges for 2DM NSFETs, including the cost-effective stacking of 2DM layers, formation of electrical contacts, suspended 2DM channels, and GAA structures, are also discussed.

Standards for the Characterization of Endurance in Resistive Switching Devices.

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Unipolar Parity of Ferroelectric-Antiferroelectric Characterized by Junction Current in Crystalline Phase Hf1-xZrxO2 Diodes.

Ferroelectric (FE) Hf1-xZrxO2 is a potential candidate for emerging memory in artificial intelligence (AI) and neuromorphic computation due to its non-volatility for data storage with natural bi-stable characteristics. This study experimentally characterizes and demonstrates the FE and antiferroelectric (AFE) material properties, which are modulated from doped Zr incorporated in the HfO2-system, with a diode-junction current for memory operations. Unipolar operations on one of the two hysteretic polarization branch loops of the mixed FE and AFE material give a low program voltage of 3 V with an ON/OFF ratio >100. This also benefits the switching endurance, which reaches >109 cycles. A model based on the polarization switching and tunneling mechanisms is revealed in the (A)FE diode to explain the bipolar and unipolar sweeps. In addition, the proposed FE-AFE diode with Hf1-xZrxO2 has a superior cycling endurance and lower stimulation voltage compared to perovskite FE-diodes due to its scaling capability for resistive FE memory devices.

Bi2O2Se-Based Memristor-Aided Logic.

The implementation of two-dimensional materials into memristor architectures has recently been a new research focus by taking advantage of their atomic thickness, unique lattice, and physical and electronic properties. Among the van der Waals family, Bi2O2Se is an emerging ternary two-dimensional layered material with ambient stability, suitable band structure, and high conductivity that exhibits high potential for use in electronic applications. In this work, we propose and experimentally demonstrate a Bi2O2Se-based memristor-aided logic. By carefully tuning the electric field polarity of Bi2O2Se through a Pd contact, a reconfigurable NAND gate with zero static power consumption is realized. To provide more knowledge on NAND operation, a kinetic Monte Carlo simulation is carried out. Because the NAND gate is a universal logic gate, cascading additional NAND gates can exhibit versatile logic functions. Therefore, the proposed Bi2O2Se-based MAGIC can be a promising building block for developing next-generation in-memory logic computers with multiple functions.

Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations.

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS2 FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.

von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of ≈75× for 1T-1R (≈40× for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of ≈3.5× for 1T-1R (≈1.6× for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU ↔ memory is observed to be ≈780× (for both SLIM bitcells).

Polymorphism Control of Layered MoTe2 through Two-Dimensional Solid-Phase Crystallization.

Two-dimensional (2D) molybdenum ditelluride (MoTe2) exhibits an intriguing polymorphic nature, showing stable semiconducting 2H and metallic 1T' phases at room temperature. Polymorphism in MoTe2 presents new opportunities in developing phase-change memory, high- performance transistors, and spintronic devices. However, it also poses challenges in synthesizing homogeneous MoTe2 with a precisely controlled phase. Recently, a new yet simple method using sputtering and 2D solid-phase crystallization (SPC) is proposed for synthesizing high-quality and large-area MoTe2. This study investigates the polymorphism control of MoTe2 synthesis using 2D SPC. The Te/Mo ratio and oxygen content in the as-sputtered films correlate strongly with the final phase and electrical properties of SPC MoTe2. Furthermore, the SPC thermal budget may be exploited for stabilizing a deterministic phase. The comprehensive experiments presented in this work demonstrate the versatile and precise controllability on the MoTe2 phase by using the simple 2D SPC technique.

Programmable Synaptic Metaplasticity and below Femtojoule Spiking Energy Realized in Graphene-Based Neuromorphic Memristor.

Memristors with rich interior dynamics of ion migration are promising for mimicking various biological synaptic functions in neuromorphic hardware systems. A graphene-based memristor shows an extremely low energy consumption of less than a femtojoule per spike, by taking advantage of weak surface van der Waals interaction of graphene. The device also shows an intriguing programmable metaplasticity property in which the synaptic plasticity depends on the history of the stimuli and yet allows rapid reconfiguration via an immediate stimulus. This graphene-based memristor could be a promising building block toward designing highly versatile and extremely energy efficient neuromorphic computing systems.

Internal current amplification induced by dielectric hole trapping in monolayer MoS2 transistor.

Carrier transport in layered transition-metal dichalcogenides is highly sensitive to surrounding charges because of the atomically thin thickness. By exploiting this property, we report a new internal current amplification mechanism through positive feedback induced by dielectric hole trapping in a MoS2 back-gate transistor on a tantalum oxide substrate. The device exhibits an extremely steep subthreshold slope of 17 mV/decade, which is strongly dependent on the substrate material and drain bias. The steep subthreshold slope is attributed to the internal current amplification arising from the positive feedback between hole generation in MoS2 triggered by large lateral electric field and Schottky barrier narrowing induced by localized hole trapping in tantalum oxide near the source contact.

3D Ta/TaO x /TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications.

The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaO x /TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.

Optically initialized robust valley-polarized holes in monolayer WSe2.

A robust valley polarization is a key prerequisite for exploiting valley pseudospin to carry information in next-generation electronics and optoelectronics. Although monolayer transition metal dichalcogenides with inherent spin-valley coupling offer a unique platform to develop such valleytronic devices, the anticipated long-lived valley pseudospin has not been observed yet. Here we demonstrate that robust valley-polarized holes in monolayer WSe2 can be initialized by optical pumping. Using time-resolved Kerr rotation spectroscopy, we observe a long-lived valley polarization for positive trion with a lifetime approaching 1 ns at low temperatures, which is much longer than the trion recombination lifetime (∼10-20 ps). The long-lived valley polarization arises from the transfer of valley pseudospin from photocarriers to resident holes in a specific valley. The optically initialized valley pseudospin of holes remains robust even at room temperature, which opens up the possibility to realize room-temperature valleytronics based on transition metal dichalcogenides.

Fully parallel write/read in resistive synaptic array for accelerating on-chip learning.

A neuro-inspired computing paradigm beyond the von Neumann architecture is emerging and it generally takes advantage of massive parallelism and is aimed at complex tasks that involve intelligence and learning. The cross-point array architecture with synaptic devices has been proposed for on-chip implementation of the weighted sum and weight update in the learning algorithms. In this work, forming-free, silicon-process-compatible Ta/TaOx/TiO2/Ti synaptic devices are fabricated, in which >200 levels of conductance states could be continuously tuned by identical programming pulses. In order to demonstrate the advantages of parallelism of the cross-point array architecture, a novel fully parallel write scheme is designed and experimentally demonstrated in a small-scale crossbar array to accelerate the weight update in the training process, at a speed that is independent of the array size. Compared to the conventional row-by-row write scheme, it achieves >30× speed-up and >30× improvement in energy efficiency as projected in a large-scale array. If realistic synaptic device characteristics such as device variations are taken into an array-level simulation, the proposed array architecture is able to achieve ∼95% recognition accuracy of MNIST handwritten digits, which is close to the accuracy achieved by software using the ideal sparse coding algorithm.

Characterization and Modeling of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device.

A two-terminal analog synaptic device that precisely emulates biological synaptic features is expected to be a critical component for future hardware-based neuromorphic computing. Typical synaptic devices based on filamentary resistive switching face severe limitations on the implementation of concurrent inhibitory and excitatory synapses with low conductance and state fluctuation. For overcoming these limitations, we propose a Ta/TaOx/TiO2/Ti device with superior analog synaptic features. A physical simulation based on the homogeneous (nonfilamentary) barrier modulation induced by oxygen ion migration accurately reproduces various DC and AC evolutions of synaptic states, including the spike-timing-dependent plasticity and paired-pulse facilitation. Furthermore, a physics-based compact model for facilitating circuit-level design is proposed on the basis of the general definition of memristor devices. This comprehensive experimental and theoretical study of the promising electronic synapse can facilitate realizing large-scale neuromorphic systems.

Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory.

Three-dimensional vertical resistive-switching random access memory (VRRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive storage-class memory technology, including low bit cost, fast access time, low-power nonvolatile storage,and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 10³ with a sub-µA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 10¹5 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage memory by exploiting a unique tradeoff between retention time and endurance.